OTL (Output Latch) sets its bit to 1 when the rung goes true and leaves it set; OTU (Output Unlatch) clears the same bit to 0 — together they form the retentive set/reset pair of ladder logic.
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How it works
OTL and OTU only ever write in one direction, and only when their rung is true. A true OTL rung writes a 1; a false OTL rung writes nothing at all — that is the crucial difference from OTE, which writes 0 on false rungs. Once latched, the bit stays 1 through false rungs, through the rung not being scanned, and — if the tag is retentive — through a power cycle. Nothing clears it except an OTU (or something else that writes the bit: an OTE, a MOV, an HMI write).
The pair always addresses the same bit from two different rungs: a latch rung with the set conditions and an unlatch rung with the clear conditions. Because each rung only acts when true, there is a real question of what happens when both are true on the same scan — and the answer is mechanical, not mysterious: instructions execute in scan order, so the rung that executes later wins. Put the OTU rung after the OTL rung and a simultaneous set/reset resolves to "reset wins", which is the safe convention for alarms and faults.
What is a latch actually for? State that must outlive its cause. A fault bit must stay on after the fault condition disappears so an operator can see what tripped. A "part present in zone 3" flag must survive while the part is between sensors. A batch-complete flag must persist until the next batch starts. In each case the set event is momentary but the state is durable — exactly the shape OTL/OTU models.
The cost of that power is that latched bits carry responsibility. Every OTL must have a matching OTU somewhere (the cross-reference tool shows you); the unlatch conditions must cover every path the process can take, including power-up. A latched output that re-energizes a motor the instant power returns after an outage is a genuine safety hazard — which is why standards work (and plain good practice) says: latch state and alarms freely, but be extremely deliberate about latching physical actuator outputs.
Across vendors
| Platform | Name / syntax | Notes |
|---|---|---|
| Allen-Bradley (Studio 5000 / RSLogix) | OTL / OTU | Coils drawn as (L) and (U). Retentivity through power loss follows the tag/processor configuration. |
| IEC 61131-3 (CODESYS, OpenPLC) | Set / Reset coils (S) (R) | Graphical -(S)- and -(R)- coils in LD; Structured Text offers the SR / RS function blocks, which make the set-dominant or reset-dominant choice explicit. |
| Siemens (TIA Portal) | S / R | The -(S)- and -(R)- coils in LAD, plus the SR / RS flip-flop boxes. RS is reset-dominant; SR is set-dominant — pick deliberately. |
| Mitsubishi (GX Works) | SET / RST | SET M10 latches bit M10; RST M10 clears it. RST also resets timers, counters and data registers. |
The IEC SR/RS function blocks answer "what if set and reset are true together" by name (set-dominant vs reset-dominant). With plain OTL/OTU coils the same question is answered by rung order — whichever executes later in the scan wins.
In practice
| Overtemp Fault_Latch | |----] [--------------------------------------(L)------| | Reset_PB Overtemp Fault_Latch | |----] [----------]/[-------------------------(U)------|
The Overtemp condition may last half a second, but the fault must be visible until a human acknowledges it: the OTL latches Fault_Latch on the first hot scan. The unlatch rung requires both the reset button and the condition to be gone — the XIO on Overtemp stops an operator from blindly resetting a fault that is still active. This latch-with-qualified-reset shape is the backbone of every alarm handler.
| Entry_Eye Part_In_Zone | |----] [---------------------------------------(L)------| | Exit_Eye Part_In_Zone | |----] [---------------------------------------(U)------|
Between the entry photo-eye and the exit photo-eye the part is invisible to both sensors — the latched Part_In_Zone bit is the only memory that it exists. The entry eye sets it, the exit eye clears it, and any rung in the program can examine it meanwhile.
Note what happens on power-up: if the tag is retentive, the flag correctly survives an outage with a part stranded in the zone. That is the argument for latching state bits — the process memory matches physical reality after a restart.
Gotchas
An OTL with no matching OTU
The bit latches on the first true scan and can never be cleared by the program — everything downstream of it is now permanently enabled. Before commissioning, cross-reference every OTL and confirm a reachable OTU exists for the same tag.
Latching a motor or valve output directly
A latched physical output re-energizes as soon as power and scanning return, with no operator action. After a power blip the machine restarts itself. Latch the request or the state, and drive the actuator through a non-retentive OTE rung that includes the safety conditions.
Ignoring set/reset priority
When both rungs are true in the same scan, the later rung wins. If the OTL rung sits below the OTU rung, your "reset" mysteriously loses whenever the set condition persists. Keep OTU rungs after OTL rungs (reset-dominant) unless you have a documented reason not to.
Mixing OTE and OTL/OTU on the same bit
The OTE re-writes the bit every scan and will stomp the latch (or fight it, depending on rung order). A bit is either latch-controlled or OTE-controlled — never both.
Assuming latched equals retentive through power loss
OTL keeps the bit set while the controller runs, but surviving a power cycle depends on the tag and controller configuration. If the latch must persist through outages, verify the tag is retentive rather than assuming.
Drop the instruction on a rung in the browser simulator, toggle the inputs, and watch the rung state, accumulator values and outputs update scan by scan.
Questions
OTE writes its bit on every scan — 1 for a true rung, 0 for a false rung — so it is non-retentive. OTL writes only a 1 and only when its rung is true; the bit then holds until an OTU (whose rung writes only a 0) clears it. OTL/OTU give you memory; OTE gives you a live reflection of the rung.
Each executes when scanned, so within one scan the bit is set by the OTL rung and cleared by the OTU rung (or vice versa) — the instruction that executes later in the scan order determines the value that survives to the end of the scan. Placing the OTU rung later makes the pair reset-dominant, which is the usual safe choice.
IEC 61131-3 ladder uses Set and Reset coils, drawn -(S)- and -(R)-, and Structured Text offers SR (set-dominant) and RS (reset-dominant) flip-flop function blocks. Siemens TIA Portal has the same S/R coils and SR/RS boxes; Mitsubishi uses the SET and RST instructions.
Only if the underlying tag is retentive. The OTL instruction itself just refrains from writing 0 on false rungs; whether the stored 1 survives power loss is decided by the tag/memory configuration of the controller. Check it explicitly whenever a latch is doing safety- or process-critical memory work.