Why an Instruction List simulator still has value
Instruction List is a compact, accumulator-oriented PLC language found in older systems, course notes and maintenance work. Reading it well means tracking the result of each load, Boolean operation and store.
New projects are generally better served by current supported languages and the target vendor’s tooling. This workbench exists to make legacy logic observable and to help learners compare common IL ideas with vendor mnemonics.
Address translation sheet
Read the memory map before the rung
These are the address forms this learning runtime recognises. The final column states the simulator behavior, including intentional simplifications.
| Device / area | Role | Example | Browser behavior |
|---|---|---|---|
| %I | Located input | %I0.0 | Binds a declared Boolean to the browser input bus. |
| %Q | Located output | %Q0.0 | Binds a declared Boolean to the browser output bus. |
| %M | Internal bit memory | %M0.0 | Provides located internal Boolean state. |
| %MW | Internal word memory | %MW0 | Provides word storage for supported data operations. |
| Symbolic | Named variable / FB | MotorRun, Delay1 | VAR declarations provide types and optional initial values. |
Executable now
Supported instruction groups
- Accumulator logic
- LD, LDN, AND, ANDN, OR, ORN and NOT
- Grouping and stores
- AND(, OR(, ), ST, STN, S and R
- Function blocks
- CAL for selected timers, counters and edge triggers
- Data operations
- MOV, ADD, SUB, MUL and DIV as standalone operations
Do not assume
Not in the current subset
- XOR and XORN
- Every vendor’s IL extensions or legacy project format
- Hardware-specific memory, scan timing and task behavior
- Importing or downloading controller projects
Worked example
A typed IEC IL motor permissive
VAR binds readable symbols to I/O. The instruction sequence loads Start, ANDs the inverse of Stop, then stores the result in Motor.
Run your own programVAR
Start AT %I0.0 : BOOL;
Stop AT %I0.1 : BOOL;
Motor AT %Q0.0 : BOOL;
END_VAR
LD Start
ANDN Stop
ST MotorLearning sequence
How to read Instruction List without guessing
- 01
Mark declarations
Record each variable type and located address before following instructions.
- 02
Track the accumulator
Write down the result after every LD, AND, OR or NOT.
- 03
Locate side effects
Identify ST/STN outputs, S/R latches and CAL function-block calls.
- 04
Translate for maintenance
Restate the logic as a Boolean expression or ladder rung, then validate against the target controller.
Engineering boundary
A learning interpreter for legacy logic
The simulator implements a documented IL subset in its own runtime. It is not a compiler for a specific controller and should not be used to claim binary or timing equivalence.
- Unsupported instructions fail rather than being guessed.
- Vendor extensions belong on their dedicated dialect pages.
- Production migration requires the target vendor’s compiler, tests and hardware validation.
Technical evidence
Sources and verification
Page claims and the simulator support matrix were reviewed against the production parser and these primary technical sources on 24 July 2026.
Continue through the cluster
Related programming and simulator guides
Delta PLC programming
See WPLSoft/ISPSoft-style mnemonics and X/Y device mapping.
Mitsubishi PLC programming
Compare GX-style LD/OUT instructions and MELSEC devices.
Omron PLC programming
Compare CX-style mnemonics and channel-bit addresses.
Schneider PLC simulator
Practise IEC and legacy Modicon address forms.
PLC Instruction List Simulator FAQ
Make legacy Instruction List observable
Run the typed example, trace the accumulator, and compare the result with the vendor dialect you maintain.