Start with the Mitsubishi device model
MELSEC programs use compact device names throughout the logic. X and Y identify physical I/O, M is internal bit memory, D is word data, and T/C identify timer and counter instances. Reading those areas confidently is more valuable than memorising menu clicks.
GX Works2 and GX Works3 cover different generations and workflows. This page focuses on transferable program-reading and instruction skills; the linked software guide covers official downloads and platform selection.
Address translation sheet
Read the memory map before the rung
These are the address forms this learning runtime recognises. The final column states the simulator behavior, including intentional simplifications.
| Device / area | Role | Example | Browser behavior |
|---|---|---|---|
| X | Discrete input | X0, X1, X8 | The simulator deliberately uses decimal bit indexing: X8 maps to %I1.0. |
| Y | Discrete output | Y0, Y7, Y8 | Maps to runtime output bytes using decimal indexing. |
| M | Internal relay | M0, M100 | Maps into internal bit memory such as %M0.0. |
| D | Data register | D0, D100 | Maps into word memory such as %MW0. |
| T / C | Timer / counter | OUT T0 K30, OUT C0 K10 | Uses a fixed 100 ms timer base and literal counter preset. |
Executable now
Supported instruction groups
- Contacts and coils
- LD, LDI, AND, ANI, OR, ORI and OUT
- Block logic
- ANB and ORB
- Latching
- SET and RST
- Data operations
- MOV, ADD, SUB, MUL and DIV as standalone operations
Do not assume
Not in the current subset
- MPS, MRD and MPP branch-stack instructions
- TOF and CTD in the Mitsubishi mnemonic parser
- Exact octal/hex addressing rules of every MELSEC family
- GX project files, hardware configuration and controller download
Worked example
A GX-style motor permissive
The first rung seals the start request into M0 until X1 breaks the path; the second mirrors that internal relay to Y0. It runs in the Mitsubishi parser.
Run your own program; M0 seals in the motor request
LD X0
OR M0
ANI X1
OUT M0
LD M0
OUT Y0Learning sequence
From device names to a maintainable MELSEC program
- 01
Separate physical and internal devices
Mark X/Y as field I/O and M/D as program memory before following any branches.
- 02
Trace the result of each instruction
Follow the result-of-logic operation through LD, AND/ANI, OR/ORI and OUT.
- 03
Add timers, counters and data
Practise T/C done states and basic D-register moves without hiding the sequence in a large project.
- 04
Recreate it in GX Works
Select the real CPU, check its address rules, configure hardware and commission through Mitsubishi’s tools.
Engineering boundary
GX-style practice is not GX Works emulation
The browser parser models a useful Mitsubishi mnemonic subset. It intentionally normalises some addressing and timing behavior so exercises remain deterministic across the training runtime.
- X/Y device mapping here uses decimal bit indexing, which may differ from the target MELSEC family.
- The fixed timer base is a learning simplification, not a controller timing specification.
- GX Works remains required for real project files, diagnostics and hardware transfer.
Technical evidence
Sources and verification
Page claims and the simulator support matrix were reviewed against the production parser and these primary technical sources on 24 July 2026.
Continue through the cluster
Related programming and simulator guides
Mitsubishi PLC Programming FAQ
Turn Mitsubishi device notation into working logic
Practise the supported GX-style subset in the browser, then transfer the reasoning into the correct MELSEC project.