PLC Simulator
Omron address and mnemonic guideProgramming guide

Omron PLC Programming: CX Addresses, Instructions and Examples

Learn Omron channel-bit I/O, W and H memory, D words, CX-Programmer mnemonics and a first motor-control sequence using examples that match the browser parser.

Run your first PLC program — no signupStudy the address map

Independent learning tool. No hardware connection, vendor project import or controller download. Technical scope verified August 7, 2026.

Program memory
Omron mnemonic
; 0.00 = start, 0.01 = stop, 100.00 = motorLD       0.00AND NOT  0.01OUT      100.00
INPUTOUTPUT

Supported Omron practice path

Every capability below is tied to the current parser instead of a generic vendor claim.

  • 0.00 and 100.00 channel-bit I/O
  • W, H and D memory areas
  • CX-style LD / AND NOT / OUT
  • TIM, CNT and basic data operations
Real Omron PLC programming footage

See this exact skill in the working simulator.

Watch the real browser product respond to the task on this page, then try the same practical workflow yourself. No slides, concept mockups, install, or credit card.

Try this in the browser
Omron PLC Simulator — Practice Sysmac-Style PLC Logic Online

Six Omron programming skills in context

Turn channel-bit addresses into observable machine behavior

Use the visual sequence to connect Omron’s memory areas to a real control task: map the I/O channels, build a start/stop circuit, add timer and counter behavior, work with D words, and then verify the program in the correct official toolchain.

Generic white PLC programming bench with ladder logic, wired controls and output lights for Omron CX-style practice
01Make the scan visible on a small training bench before navigating a larger CX-Programmer project.
PLC channel-bit addressing panel with separated 16-point input and output banks and internal memory indicators
02Read 0.xx input and 100.xx output channels as groups of sixteen bits, then keep W, H and D memory distinct.
Motor starter training panel with pushbuttons, PLC, contactor, overload and motor for Omron ladder practice
03Build a start/stop path and explain why the normally-closed condition must remain true for the motor to run.
Bottle conveyor PLC lab with sensor and stack light for Omron TIM and CNT instruction practice
04Apply TIM and CNT to an observable conveyor event instead of memorizing instructions in isolation.
PLC pressure process lab with engineering display and test instruments for Omron D-memory exercises
05Move and calculate D-word values, then confirm the resulting process state with a real measurement.
Instructor and learner safely validating a guarded conveyor PLC cell at an engineering workstation
06Choose CX-Programmer or Sysmac Studio for the actual CPU and complete model-specific validation before commissioning.

Omron programs become easier once the memory areas are clear

Older CJ/CS-era projects commonly use CX-Programmer conventions, including channel-bit addresses such as 0.00 and 100.00. W and H areas provide internal bit storage, while D identifies word data.

Newer NJ/NX projects use Sysmac Studio and a more tag-oriented workflow. The browser’s Omron dialect is deliberately focused on the CX-style mnemonic and address patterns documented below.

Address translation sheet

Read the memory map before the rung

These are the address forms this learning runtime recognises. The final column states the simulator behavior, including intentional simplifications.

Device / areaRoleExampleBrowser behavior
0.00–99.15Input channel bits0.00, 1.15Maps to runtime input channels; bit positions are limited to 00–15.
100.00–199.15Output channel bits100.00, 101.15Maps to runtime outputs after subtracting the 100-channel offset.
WWork bitsW0.00Maps to internal bit memory for intermediate logic.
HHolding bitsH0.00Runs as a separate internal bit area for address practice.
DData memory wordsD0, D100Maps into word memory for MOV and arithmetic instructions.

Executable now

Supported instruction groups

Contacts
LD, LD NOT, AND, AND NOT, OR and OR NOT
Outputs and latches
OUT, OUT NOT, SET and RSET
Timing and counting
TIM and CNT with a fixed 100 ms timer base
Data operations
MOV, ADD, SUB, MUL and DIV as standalone operations

Do not assume

Not in the current subset

  • AND LD and OR LD block-combine instructions
  • TOF and CTD
  • Exact BCD behavior—the # preset marker is simplified to decimal
  • PLC model configuration, networks, task scheduling and controller transfer

Worked example

An Omron channel-address motor rung

The input channel bits feed a normally-open start and normally-closed stop condition before the output channel. The example is accepted by the Omron parser.

Run your own program
Omron mnemonicParser-valid example
; 0.00 = start, 0.01 = stop, 100.00 = motor
LD       0.00
AND NOT  0.01
OUT      100.00

Learning sequence

A sensible Omron study sequence

  1. 01

    Translate the addresses

    Label input channels, output channels, work bits, holding bits and data words.

  2. 02

    Read CX mnemonics aloud

    Say “load,” “and not,” and “output” while following the logic result.

  3. 03

    Add memory and sequence

    Use W/H state, then TIM and CNT with deliberately small presets.

  4. 04

    Choose the real toolchain

    Match CX-Programmer or Sysmac Studio to the actual CPU and validate with its manuals.

Engineering boundary

CX-style teaching subset, not a complete Omron runtime

The simulator teaches a useful address and instruction subset. It does not reproduce an Omron PLC model, exact memory retention, BCD execution or the full instruction catalog.

  • Treat # timer presets as the simulator’s simplified decimal input.
  • Confirm memory allocation and retention on the exact Omron CPU.
  • Use official engineering software for projects, communications and commissioning.

Technical evidence

Sources and verification

Page claims and the simulator support matrix were reviewed against the production parser and these primary technical sources on August 7, 2026.

Continue through the cluster

Related programming and simulator guides

Omron PLC simulator

Run the supported CX-style subset and inspect its boundaries.

Omron PLC software guide

Compare CX-Programmer and Sysmac Studio paths.

Mitsubishi PLC programming

Compare another widely encountered Japanese PLC convention.

Questions

Omron PLC Programming FAQ

In the simulator’s CX-style channel map, 100.00 is the first output bit. Addresses below channel 100 map to inputs and 100–199 map to outputs.

Practice Omron addresses until they read naturally

Run a small channel-address program, then add W/H state, timers, counters and D-register operations.

Run your first PLC program — no signupCompare all dialects

Vendor-dialect field guide

Omron PLC programming: memory, workflow and tested boundaries

Direct answer

Omron PLC programming begins with an accurate memory and I/O model. Learn CIO channel/bit I/O, W and H work areas, D data memory, timers and counters. Build a small observable program, monitor the exact devices over scans and verify target-specific syntax, retentive behavior and download procedure in the official environment.

This guide is written for learners transferring vendor-neutral PLC reasoning into a named controller ecosystem without confusing mnemonic familiarity with full platform competence. The intended result is specific: the learner can read common Omron-style addresses, trace a start/stop or timed sequence and explain which behaviors still require the exact controller and engineering software.

System map / 02

NODE 01observable

Device and address

Separate physical I/O, internal Boolean state, numeric data, timer/counter state and special/system areas within CIO channel/bit I/O, W and H work areas, D data memory, timers and counters.

NODE 02observable

Program scan

Follow the same input-read, logic-execution and output-update reasoning while confirming platform-specific task and refresh details.

NODE 03observable

Symbolic naming

Use meaningful symbols and comments even when maintenance requires device addresses to remain visible.

NODE 04observable

Retentive state

Confirm which areas and instructions retain state through mode change or power cycle for the exact CPU configuration.

NODE 05observable

Online observation

Monitor device state to compare input, logic result, output command and feedback without treating a forced value as normal operation.

NODE 06observable

Transfer boundary

Use CX-Programmer and Sysmac-family conventions require model-specific confirmation; repeat syntax, compile, download, timing and I/O tests before real deployment.

Procedure / 03

  1. 01

    Choose the CPU context

    Record controller family, software and firmware assumptions.

    Evidence: The exercise has a target boundary.

    Avoid: Writing “all models” instructions.

  2. 02

    Map the devices

    Assign the example using CIO channel/bit I/O, W and H work areas, D data memory, timers and counters.

    Evidence: Every address has one engineering role.

    Avoid: Reusing a device for unrelated state.

  3. 03

    Write normal behavior

    Build one start/stop or sequence requirement.

    Evidence: The program is readable and observable.

    Avoid: Translating mnemonics without intent.

  4. 04

    Monitor scans

    Toggle inputs and watch devices, timers and outputs.

    Evidence: State matches the predicted table.

    Avoid: Using force as permanent logic.

  5. 05

    Test reset and restart

    Exercise stop, fault, mode change and initialization.

    Evidence: Retained and cleared state is explicit.

    Avoid: Assuming simulator persistence matches CPU memory.

  6. 06

    Verify officially

    Open the equivalent project in the supported vendor tool and hardware path.

    Evidence: Compile and runtime evidence is target-specific.

    Avoid: Treating browser success as commissioning.

Diagnostic matrix / 04

Diagnostic symptoms, inspection points, interpretations and next actions for Omron PLC programming: memory, workflow and tested boundaries
Observed symptomInspectInterpretationNext proving action
Input address never changesPhysical mapping, channel/device address, refresh and force stateThe program may read a different device than the wired point.Verify the hardware map.
Internal bit changes unexpectedlyEvery writer, special-area overlap and initializationMemory ownership is unclear.Cross-reference writes.
Timer behavior differsTime base, instance/device, retentive semantics and task timingSimilar mnemonics can have platform differences.Use the exact instruction help.
Value is corruptRegister width, signedness, word order and conversionThe same device words can represent different types.Inspect typed interpretation.
Download/run differsCPU mode, compile warnings, retained values and I/O refreshEditor simulation did not reproduce controller state.Repeat on a controlled target.
Fault returns after resetActive cause, diagnostic buffer and reset permissivesReset is not removal of cause.Read the official diagnostic record.

Product evidence / 05

What the browser practice can actually demonstrate

The browser dialect page provides parser-tested examples, mapped memory concepts, runnable scenarios and an explicit boundary: CX-Programmer and Sysmac-family conventions require model-specific confirmation.

Answer surface / 07

Can I learn this PLC family online?

Yes. Learn CIO channel/bit I/O, W and H work areas, D data memory, timers and counters, common instructions and monitoring concepts online, then use official software and hardware for platform competence.

Is this the official vendor simulator?

No. It is CX-Programmer and Sysmac-family conventions require model-specific confirmation.

Do device addresses work the same on every model?

No. CPU families, modules and software generations vary. Confirm the exact manuals.

Can I import this project into vendor software?

Do not assume project-file compatibility. Recreate and verify the example in the official environment.

Which program should I build first?

Use a start-stop circuit with stop priority, then a timer or counter scenario with explicit reset.

Why are symbols still important?

Symbols preserve engineering meaning while device addresses satisfy the platform mapping.

Can a browser test prove real I/O?

No. It proves the learning runtime behavior; physical I/O and task behavior need target tests.

Does the vendor endorse this page?

No. Vendor names and trademarks identify independent educational context.

Omron learning path

Connect channel-bit addressing to machine behavior

Use one path for the executable subset, memory areas, official software handoff and a comparable vendor mnemonic system.